Single transistor RAM cell and method of manufacture

ABSTRACT

A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to leave an unetched spacer dielectric layer portion overlying the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; and, carrying out a second ion implantation process to form a relatively higher dopant concentration in a second portion of the second doped region.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor devicemanufacturing methods and more particularly to a single transistor DRAMmemory cell with reduced size and increased Voltage retention timeincluding a method for manufacturing the same.

BACKGROUND OF THE INVENTION

Dynamic random access memories (DRAM) are useful for maximizing thenumber of bits stored per unit surface area. In particular, a singletransistor (1T) DRAM cell includes a single MOS transistor, alsoreferred to as a pass transistor or an access transistor, which isconnected to a word line which is used to switch the pass transistor onor off to thereby couple or decouple a bit line to a storage capacitor.When the storage capacitor is charged to a predetermined Voltage, thememory cell stores a “1” state. When the storage capacitor is charged toa lower predetermined Voltage, typically ground, the memory cell storesa “0” state.

The Voltage stored, e.g., as a “1” state in the memory cell decays overtime to a lower “0” state Voltage (e.g., ground Voltage) through variousleakage mechanisms. Unlike the charge replenishing process for staticRAM, the only way to maintain the information in DRAM is by periodicallyreading and rewriting the data through a “refresh” operation. Avoidingcurrent leakage and thereby maintaining charge retention in a DRAM cellis extremely important for scaling down memory cell size.

Several leakage mechanisms can affect the stored charge in DRAM cellsincluding junction leakage, pass transistor threshold leakage andleakage through the storage capacitor dielectric as well as otherparasitic leakage paths. In particular, prior art memory 1T DRAM memorycells, including for example, planar storage capacitors haveunacceptable charge retention times for future applications at requiredmemory cell densities.

Therefore, there is a continuing need in the DRAM processing art todevelop a DRAM memory cell with improved charge retention time andreduced size while avoiding undue manufacturing cost.

It is therefore among the objects of the invention to provide a DRAMmemory cell with improved charge retention time and reduced size whileavoiding undue manufacturing cost, in addition to overcoming othershortcomings and deficiencies of the prior art.

SUMMARY OF THE INVENTION

To achieve the foregoing and other objects, and in accordance with thepurposes of the present invention, as embodied and broadly describedherein, the present invention provides a single transistor RAM cellstructure with improved charge retention and method for forming thesame.

In a first embodiment, the method includes providing a silicon substratecomprising an STI structure and an overlying dielectric gate layer;depositing a polysilicon layer; forming a pass transistor structureadjacent a storage capacitor structure separated by a predetermineddistance; carrying out a first ion implantation process to form firstand second doped regions adjacent either side of the pass transistorstructure, the first doped region defined by the predetermined distance;depositing a spacer dielectric layer; etching back the spacer dielectriclayer to leave an unetched spacer dielectric layer portion overlying thefirst doped region while forming a sidewall spacer of a predeterminedwidth overlying a first portion of the second doped region; and,carrying out a second ion implantation process to form a relativelyhigher dopant concentration in a second portion of the second dopedregion.

These and other embodiments, aspects and features of the invention willbe better understood from a detailed description of the preferredembodiments of the invention which are further described below inconjunction with the accompanying Figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1F are cross sectional views of a portion of a singletransistor DRAM memory cell at stages in production according to anembodiment of the invention.

FIG. 2 is a process flow diagram including several embodiments of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Although the method of the present invention is explained with referenceto the formation of a planar storage capacitor with an oxide dielectric,it will be appreciated that the 1T DRAM cell of the present inventionmay be formed using other capacitor dielectric materials including highdielectric constant materials, for example having a dielectric constantof greater than about 10.

Referring to FIG. 1A is shown a cross sectional view of a portion of aprocess wafer having formed therein an exemplary shallow trenchisolation (STI) structure 14 formed by conventional processes in a Pdoped silicon substrate 12, having a P-doped region 12A and an N-welldoped region 12B formed adjacent to the STI structure 14 in an activeregion of the device. Although the formation and preferred embodiment asshown in the Figures is of a PMOS pass transistor type DRAM memory cell,it will be appreciated that the NMOS pass transistors may be formed aswell with appropriate differences in the type of dopant e.g., N orP-type dopants, as is known in the art.

Still referring to FIG. 1A, the STI structure 14 formation processbegins with the formation of a pad oxide layer (not shown) thermallygrown over the silicon substrate 12, for example formed by conventionaldry or wet thermal oxidation methods, followed by formation of anoverlying nitride layer (not shown), for example silicon nitride (e.g.,Si₃N₄) formed by a conventional CVD, e.g., LPCVD process. A conventionallithographic and etching process is then carried out whereby the nitridelayer and pad oxide layer are first etched to form a hard mask followedby etching an STI trench with preferred properties including havingsidewalls at an angle from about 70 to about 85 degrees and havingrounded bottom corners to reduce stress. An oxide liner (not shown) isthen thermally grown to line the trench (not shown) followed bybackfilling with silicon oxide (e.g., SiO₂) by e.g., an HDP-CVD process,also referred to as STI oxide.

The STI oxide is then planarized by a CMP process to stop on the siliconnitride layer (not shown) followed by removal of the silicon nitridelayer and pad oxide layer by a conventional wet stripping, e.g., hotH₃PO₄, and HF respectively, to leave the STI oxide structure 14. Asacrificial oxide layer (not shown) is then thermally grown over thesilicon substrate to modify a subsequent high energy (e.g. 500 keV to 1MeV) ion implant, e.g., phosphorous, to form an N-well region, e.g.,12B. Following conventional masking and ion implantation processes,(e.g., retrograde well and V_(t) adjustment implants) the N-well region12B is formed followed by removal of oxides overlying the siliconsubstrate 12 by a conventional HF wet stripping process. The siliconsubstrate 12 is then cleaned by conventional processes, for example,using standard cleaning 1 (SC-1) and/or standard cleaning-2 (SC-2)solutions, including mixtures of NH₄OH—H₂O₂—H₂O, and HCl—H₂O₂—H₂O,respectively.

Referring to FIG. 1B, a gate dielectric layer or stack e.g., 18, isformed over the silicon substrate 12. For example a thermally grown gateoxide (e.g., SiO₂) layer may be suitably used as the gate dielectric,for example, thermally grown by wet or dry methods at temperatures fromabout 900° C. to about 1150° C. and preferably having a thickness offrom about 20 to about 50 Angstroms. It will be appreciated that thegate oxide layer e.g., 18 may be subjected to nitridation techniquessuch as nitrogen containing plasma and/or annealing treatments toincrease the dielectric constant. In addition, alternating layers ofsilicon oxide/silicon nitride or silicon oxynitride, also referred to asan oxide/nitride gate dielectric may be formed as the gate dielectricstack e.g., 18.

In addition, one or more layers of a high-K dielectric (e.g., dielectricconstant greater than about 10), for example, tantalum pentaoxide (e.g.,Ta₂O₅) may be used to form the gate dielectric 18. Other metal oxidessuch as, titanium oxides, (e.g., TiO₂), hafnium oxides (e.g., HfO₂),yttrium oxides (e.g., Y₂O₃), lanthanum oxides (e.g., La₂O₅), zirconiumoxides (e.g., ZrO₂), and silicates and aluminates thereof may also besuitably used to form the gate dielectric 18, for example having anequivalent oxide thickness (EOT) of an SiO₂ gate dielectric, e.g.,having a thickness of from about 50 Angstroms to about 200 Angstromsformed over a thermally grown interfacial oxide layer (not shown) formedover the silicon substrate 12. For example, atomic layer chemical vapordeposition (ALCVD) methods, followed by annealing treatments in oxygen,nitrogen and/or hydrogen may be used to from a high-K gate dielectriclayer stack. Further, other high dielectric constant materials, such asBaSrTiO₃ (BST), and PbZrTiO₃ (PZT) or other high-K materials, preferablyhaving a dielectric constant greater than about 10, more preferablyabout 20, may be suitably used to form a high-K gate dielectric stack.

Still Referring to FIG. 1B, a polysilicon layer 20 is deposited over thegate dielectric layer 18 by conventional techniques e.g., an LPCVDprocess to a thickness of about 2000 Angstroms to about 4000 Angstroms.Preferably the polysilicon layer 20 is deposited undoped and issubsequently doped (e.g., using P-dopants, e.g., boron) simultaneouslywith an ion implantation process to form doped contact regions, e.g.,source/drain regions adjacent the pass transistor as explained furtherbelow.

Referring to FIG. 1C, a conventional photolithographic patterning andetching process is carried on the polysilicon layer 20 to define gatestructures e.g., 22A for the pass transistor and capacitor structurese.g., 22B for the storage capacitor in a DRAM memory cell. Preferablythe storage capacitor structure 22B is formed as a planar capacitor,e.g., the capacitor dielectric e.g., gate dielectric layer 18 as well asthe overlying polysilicon electrode portion (e.g., plate) is formedco-planar with the silicon substrate 12 process surface. In an importantaspect of the invention, a distance D between the pass transistorstructure, e.g., 22A and the storage capacitor 22B is selected such thatit is less than about twice, for example from about 1 times to about 1and ¾ times the width of a subsequently formed sidewall spacer asexplained and shown further below.

A conventional ion implantation doping process, also referred to as anLDD implant, is then carried to form, for example, P-doped source/drainextension (SDE) portions of P-doped regions e.g., 24A and 24B adjacenteither side of the pass transistor 22A and adjacent one side of thestorage capacitor 22B. A P-type dopant implant, for example boron, iscarried out at a dose (concentration) preferably ranging from about 10¹²to about 10¹⁴ dopant atoms/cm² to form P doped regions 24A and 24B. Itwill be appreciated that other methods to achieve a shallow implant maybe used, e.g., from about 200 Angstroms to about 1000 Angstroms indepth, depending on the scaled design of the transistor, for exampleless than about 0.25 micron CMOS technology, including less than about0.18 micron CMOS technology. For example, gas immersion laser doping andplasma immersion doping methods as are known in the art may be used,however, ion implantation methods are preferred.

Referring to FIG. 1D, in an important aspect of the invention, sidewallspacer dielectric material, for example including one or more layerse.g., 26 of silicon oxide (SiO₂), silicon nitride (e.g., SiN), andsilicon oxynitride (e.g., SiON) is deposited, for example using ablanket (e.g., substantially conformal) deposition process such asLPCVD, PECVD or HDP-CVD, to about a thickness of a desired sidewallspacer width, for example equal to or greater than the predetermineddistance D to at least partially, preferably substantially fill thespace defined by distance D between pass transistor 22A and storagecapacitor 22B. The thickness of the layer 26 for example, is betweenabout 500 Angstroms and about 2000 Angstroms.

Referring to FIG. 1E, a conventional wet or dry etchback process,preferably a dry (plasma enhanced) etchback process is then carried outto etchback sidewall spacer dielectric layer 26 to form sidewall spacerse.g., 26A and leaving a sidewall spacer layer portion 26B remainingbetween the storage capacitor 22B and the pass transistor 22A to cover Pdoped region 24B following the plasma enhanced etchback process.Advantageously, by forming pass transistor portion 22A and storagecapacitor 22B to have a predetermined distance D between the respectivestructures of less than about twice a sidewall spacer width, thesidewall spacer etchback process leaves an unetched dielectric sidewallspacer layer portion e.g., 26B, covering the P-doped region 24B therebyforming an implant mask in a subsequent ion implant process e.g., HDD,to form a more heavily doped contact region e.g., 24A.

Still referring to FIG. 1E, a second P type ion implantation process,e.g., boron, is then carried out to increase the P doping level anddepth in doped region e.g., 24A in a self aligned ion implantationprocess to form a P+ doped region in doped region 24A. The second ionimplantation process is carried out to form P+ doped region 24Apreferably at a dose (concentration) greater than about 10¹⁵ dopantatoms/cm². In an important aspect of the invention, the unetchedsidewall dielectric layer spacer portion 26B acts as an ion implant maskto block further P doping of the region 24B in the second ionimplantation process thereby forming a relatively lightly doped regions,e.g., a P− doped region 24B relative to P+ doped region 24A.

Referring to FIG. 1F, a conventional salicide (self aligned silicide)formation process is then carried out by first removing material layersoverlying the silicon substrate 12 (e.g., oxide portions), followed bydeposition of a metal, for example Ti or Co and a silicidation processto form salicides e.g., TiSi₂ or CoSi₂, 28A, 28B, and 28C respectivelyaligned over P+ doped region 24A, the pass transistor 22A, and thestorage capacitor 22B. Advantageously the unetched spacer dielectriclayer portion 26B operates to prevent salicide formation over the P−doped region 24A. Conventional process are then carried out to formappropriate conductive interconnects (not shown), for example providinga respective conductive interconnects to electrically connect to e.g.,salicide portion 28A (bit line) of P+ doped region 24A, salicide portion28B (word line) of pass transistor 22A, and salicide portion 28C ofstorage capacitor 22B.

Advantageously according to the 1T RAM structure formed according to themethod of the present invention current leakage is reduced includingjunction leakage path through the doped portion 24B from the storagecapacitor thereby increasing a charge retention time and refresh cycletime. The reduced charge (current) leakage is believed to be due to theformation of a relatively lower doping level formed at the storage noderegion e.g., doped region 24B which is advantageously accomplishedwithout additional process steps. In addition, the formation ofsalicides 28A, 28B, and 28C over desired electrical contact portions ofthe wafer is accomplished without forming a silicide portion over thestorage node region 24B, which is believed to contribute to parasiticcurrent leakage paths. As a result, the 1T RAM structure according toexemplary embodiments advantageously accomplishes increased chargeretention while reducing a memory cell size and avoiding extraprocessing steps.

Referring to FIG. 2 is a process flow diagram including severalembodiments of the present invention. In process 201, an STI structureis provided in a doped silicon substrate. In process 203 a gatedielectric is formed over the silicon substrate. In process 205, apolysilicon layer is deposited and etched to form a pass transistorstructure adjacent a storage capacitor separated by a predetermineddistance less than about twice a subsequently formed sidewall spacerwidth. In process 207, a first ion implant process is carried out toform first and second doped regions adjacent either side of the passtransistor. In process 209, a spacer dielectric layer is deposited andetched back to form a sidewall spacer over a portion (partially masking)the first doped region while leaving a spacer dielectric layer portionoverlying (fully masking) the second doped region defined by thepredetermined distance. In process 211, a second ion implantationprocess is carried to form a more heavily doped silicon region in theexposed portion of the first doped region. In process 213, a salicideformation process is carried out to form silicided regions over thefirst doped region, the pass transistor, and the storage capacitor. Inprocess 215, bit lines, word lines and storage capacitor interconnectsare formed to complete formation of a single transistor (1T) RAM memorycell.

While the embodiments illustrated in the Figures and described above arepresently preferred, it should be understood that these embodiments areoffered by way of example only. The invention is not limited to aparticular embodiment, but extends to various modifications,combinations, and permutations as will occur to the ordinarily skilledartisan that nevertheless fall within the scope of the appended claims.

1-21. (canceled)
 22. A single transistor planar RAM device comprising: apass transistor structure and a storage capacitor structure formed overa silicon substrate and disposed is spaced apart relationship to form aspaced distance overlying a first doped region; wherein sidewall spacermaterial is disposed adjacent either side of the pass transistorstructure partially covering a second doped region and fully coveringthe first doped region.
 23. The single transistor planar RAM device ofclaim 22, wherein the first doped region comprises a lower dopantconcentration compared to the second doped region.
 24. The singletransistor planar RAM device of claim 22, wherein the first doped regionis doped to a level of between about 10¹² and 10¹⁴ dopant atoms/cm² andthe second doped region comprises a relatively higher doped region ofgreater than about 10¹⁵ dopant atoms/cm².
 25. The single transistorplanar RAM device of claim 23, wherein the storage capacitor structureis disposed at least partially overlying a shallow trench isolationstructure.
 26. The single transistor planar RAM device of claim 23,further comprising salicide portions formed over a portion of the seconddoped region, the pass transistor structure, and the storage capacitorstructure.
 27. The single transistor planar RAM device of claim 23,wherein the pass transistor structure and the storage capacitorstructure comprise a dielectric gate layer selected from the groupconsisting of SiO₂, nitrided SiO₂, and oxide/nitride.
 28. The singletransistor planar RAM device of claim 23, wherein the pass transistorstructure and the storage capacitor structure comprise a dielectric gatelayer comprising material selected from the group consisting of Ta₂O₅,TiO₂, HfO₂, Y₂O₃, La₂O₅, ZrO₂, BST, and PZT.
 29. The single transistorplanar RAM device of claim 23, wherein the pass transistor structure andthe storage capacitor structure comprise a memory cell formed over an Ndoped well region formed in a P doped silicon substrate.
 30. The singletransistor planar RAM device of claim 23, wherein the first and seconddoped regions respectively comprise P− and P+ doped regions.
 31. Thesingle transistor planar RAM device of claim 23, wherein the passtransistor structure and the storage capacitor structure comprise Pdoped polysilicon electrode portions.
 32. The single transistor planarRAM device of claim 23, wherein the spacer dielectric material comprisesone or more layers selected from the group consisting of silicon oxide,silicon nitride, and silicon oxynitride.